Conventional non-volatile memory devices broadly fall into two different categories, floating gate and trapping layer. Trapping layer memory cells, such as SONOS-memories or NROM-memories, have an n-channel FET with the gate dielectric replaced by a trapping layer and two barrier layers sandwiching the trapping layer. The trapping layer is the storage element of the memory cell. The barrier layers inhibit direct tunneling of charge carriers from and to the non-conductive trapping layer. Floating gate memory cells comprise usually an n-channel FET with a floating gate sandwiched between a dielectric tunnel layer separating the floating gate from the transistors channel region and a dielectric barrier layer between the floating gate and the control gate that is connected to the address circuitry. The floating gate is the storage element of the memory cell. The tunnel dielectric and the dielectric barrier layer insulate the conductive floating gate. Each memory cell may be programmed by injecting charge carriers into the trapping layer or the floating gate from either the control gate or the channel region. The memory cell is erased by removing or compensating the previously injected charge. The embodiments of the current invention are not limited to these two different categories of non-volatile memories and may cover other types of solutions.
Memory cells may be based on a binary or a multi-level programming/sensing scheme, for example a 4-bit per cell programming/sensing scheme. According to a binary programming/sensing scheme, the n-channel FET switches from a non-conductive state to a conductive state when a read voltage applied to the control gate exceeds a threshold voltage. The n-channel FET returns to the non-conductive state when the read voltage falls below the threshold voltage. A negative charge that is stored in the trapping layer functions as a negative bias of the control gate and shifts the threshold voltage towards higher voltage values.
The state of the memory cell is detected by applying a suitable read voltage to the control gate and checking whether the FET is conductive or not. In a binary sensing scheme, the read voltage is selected such that, on one hand, the read voltage is high enough to ensure that all erased memory cells are conductive and that, on the other hand, the read voltage is low enough to ensure that none of the programmed memory cells are non-conductive.
According to a 4-bit per cell programming/sensing scheme, three different amounts of charge are trapped in the same location or equivalent amounts of charge are trapped in different locations of the trapping layer. Three different voltage levels are used to define four different ranges or states. Each of the four different ranges or states represents a unique arrangement of a pair of bits (e.g., 00, 01, 10 or 11).
The threshold voltage for each memory cell depends, to some extent, on geometric and physical properties. For example, channel length, channel doping profile, and barrier layer thickness vary from memory cell to memory cell. Each cell array with a plurality of memory cells shows a representative threshold voltage distribution. A cell array's sense window is determined by the distance between the threshold voltage distributions for the erased state of the cell array and the programmed state. Wide sensing windows minimize the number of read errors. In order to achieve wide sensing margins, the read voltage is typically set at in the middle of the sense window.
During the course of a memory's lifetime, programmed memory cells exhibit marked retention loss and the margin between the read and write voltage may become narrower. At or near the same time, the threshold voltage distribution of the erased memory cells may show a downward trend. Adjusting the read voltage to reflect the change in the sense window may ensure that there are sufficient margins between the erased and programmed state of the cell array during its operating product lifetime.
FIG. 1 is a diagram showing exemplary threshold voltage distributions for a cell array comprising a plurality of binary memory cells at the beginning and towards the end of lifetime. The diagram plots a memory cell count Nr against a test voltage Vtest for the programmed state and the erased state at the beginning and at the end of lifetime, respectively. The abscissa indicates a test voltage Vtest and is scaled to a step voltage Vstep. The ordinate indicates the respective memory cell count Nr. The dotted lines refer to threshold voltage distributions 11a, 12a at the beginning of the life cycle, while the continuous lines refer to the corresponding threshold voltage distributions 11b, 12b at the end of lifetime.
A first threshold voltage distribution 11a shows the number of erased memory cells switching to the conductive state at the respective test voltage at the beginning of the lifetime of the memory device. A second threshold voltage distribution 12a indicates the number of programmed memory cells that switch to the conductive state at the respective test voltage at the beginning of the lifetime of the memory device. Each curve 11a, 12a represents essentially a gaussian distribution, where the distribution for the programmed state may tend to be wider than the distribution for the erased state. The first curve 11a referring to erased memory cells has a lower distribution edge VtLL and an upper distribution edge VtHL. The second plot 12a referring to programmed memory cells has a lower distribution edge VtLH and an upper distribution edge VtHH.
By applying a test voltage lower than VtLL to a cell array that comprises both erased and programmed memory cells, none of the memory cells, whether programmed or erased, is conductive and no information can be obtained from the cell array. Applying a test voltage higher than VtLL but lower than VtHL would cause only a portion of the erased cells to becoming conductive. By applying a test voltage higher than VtHH, all programmed memory cells become conductive and no information can be obtained from the cell array. Applying a test voltage lower than VtHH but higher than VtLH would cause at least a portion of the programmed cells to become conductive. For determining the correct information from each memory cell, the read voltage must be within the range of an initial “sense window” W1 between VtHL and VtLH. Typically the initial application read voltage is set equal to the arithmetic mean of VtLH and VtHL at the beginning of the life cycle.
The third curve 11b and the fourth curve 12b illustrate the threshold voltage distributions of the same cell array at the end of lifetime of the cell array. Both distribution curves 11b, 12b show a shift towards smaller threshold voltages, whereby the shift is greater for the threshold voltage distribution of programmed cells. The initial read voltage Vrdinit may be outside the final sense window W2. Without adapting the application read voltage to the shift of the threshold voltage toward the end of lifetime the memory device would detect an increasing portion of the programmed bits as being erased. Setting the application read voltage near to VtLH such that the read voltage would be within both the initial sense window W1 and the final sense window W2 would increase sensitivity towards disturbances at the beginning of life time. A rough method for tracking the read voltage may be to predict the actual sense window by the number of program/erase cycles yet performed by the cell array. As a read latency should be as short as possible, the read voltage should continuously track the actual sense window.